1. Field
The described embodiments relate to computing devices. More specifically, the described embodiments relate to using a linear prediction to configure an idle state of an entity in a computing device.
2. Related Art
In many computing devices, entities (i.e., processors, processor cores, etc.) encounter idle periods, which are periods of time during which an entity is idle and does not complete computational operations. During idle periods, some of these entities select an idle state from a set of idle states and transition to the selected idle state to conserve power. For such entities, each idle state in the set of idle states has different settings for one or more operating parameters (e.g., voltages, clock frequencies, etc.) for one or more parts of the entity. For example, in some idle states, one or more controlling clocks can be reduced in frequency or halted to one or more of processing circuits, interrupt circuits, interface circuits, etc. for the entity. As another example, in some idle states, one or more input voltages can be reduced (possibly to 0V) to one or more of processing circuits, interrupt circuits, interface circuits, etc. for the entity. Some of these entities use at least some of the idle states from a well-known set of states that includes states C0-C6.
In these computing devices, transitioning an entity into and back out of some of the idle states incurs delay due to operations that are performed to enable the transition. For example, for entities that support the C0-C6 states, when transitioning from the C0 state (full power) to the C6 idle state (deep power down) a delay is incurred because architectural state such as values in registers, values in caches, state variables, etc. must be preserved by writing the architectural state to a memory (e.g., to disk, to a memory, to a lower-level cache, and/or to another location) before one or more voltages in the entity are reduced to a level lower than the level required to maintain the architectural state within the entity. As another example, when transitioning from the C6 idle state to the C0 state a delay is incurred because, after the one or more voltages are restored to levels sufficient to maintain the architectural state within the entity, preserved architectural state such as values for registers, etc. must be recovered from the memory and used to set architectural state for the entity.
Because transitioning into and back out of some idle states incurs delays, making such a transition can cause inefficient operation for the entity (and, more generally, the computing device) when the transition is made at the wrong time. For example, if an idle period is shorter than a given duration, the delay incurred for making the transitions into and back out of the idle state can be longer than the idle period, meaning that the transition results in unnecessary delay for the entity. In addition, the transition to the idle state has a cost in terms of power expended to transition into and back out of the idle state. If the idle period is not sufficiently long, the power conserved by entering the idle state can be exceeded by the power expended to transition into and back out of the idle state.
Throughout the figures and the description, like reference numerals refer to the same figure elements.